- 1 - e06233b74 this ic is esd sensitive device. s pecial handling precautions are required. sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illu strating the operation of the devices. sony cannot as sume responsibility for any problems aris ing out of the use of these circuits. CXG1215UR high power dp3t switch with logic control description the CXG1215UR can be used in wireless communicati on systems, for example, dual-band cdma handsets. this ic has on-chip logic for operation with 3 coms control inputs. the sony jphemt process is used for low insertion loss and on-chip logic circuit. (applications: antenna switch for cellular handsets, dual-band cdma) features ? low insertion loss: 0.35db@900mhz, 0.5db@2ghz ? 3 cmos compatible control line package small package size: 16-pin uqfn structure gaas jphemt mmic absolute maximum ratings (ta = 25 c) ? input power max (rf port) pin 37 dbm ? bias voltage v dd 7v ? control voltage vctl 5 v ? operating temperature topr ?35 to +85 c ? storage temperature tstg ?65 to +150 c
CXG1215UR - 2 - block diagram and re commended circuit when using this ic, the following external components should be used: c rf : this capacitor is used for rf decoupling and must be used for all applications. cbypass: this capacitor is used for dc line filtering. truth table dc bias conditions (ta = 25 c) 6 5 12 rf1 (800mhz) 11 gnd 9 gnd ctlb ctlc ctla rf2(2ghz) 13 gnd 15 3 rf4(ant) 2 gnd 1 rf5(ext) c rf 4 gnd 14 c rf 10 c rf rf3 (gps) c rf 8 16 7 gnd c rf gnd cbypass (100pf) v dd f9 f7 f11 f10 f8 f4 f3 f2 f1 f6 f5 statectlactlbctlc on state f1f2f3f4f5f6f7f8f9f10f11 1 l l h rf4 ? 1 (ant-800mhz) on off off off off off off on on off on 2 l h h rf4 ? 2 (ant-2ghz) off off on off off off on off on off on 3 h l h rf4 ? 3 (ant-gps) off off off off on off on on off off on 4 l l l rf5 ? 1 (ext-800mhz) off on off off off off off on on on off 5 l h l rf5 ? 2 (ext-2ghz) off off off on off off on off on on off 6 h l l rf5 ? 3 (ext-gps) off off off off off on on on off on off item min. typ. max. unit vctl (h) 2.0 2.6 3.2 v vctl (l) 0 ? 0.5 v v dd 2.62.853.2v
CXG1215UR - 3 - electrical characteristics (ta = 25 c) *1 pin = 25dbm, 0/2.6v control, v dd = 2.85v, 890 to 930mhz *2 pin = 25dbm, 0/2.6v control, v dd = 2.85v, 1.92 to 1.98ghz *3 pin = 25dbm (900mhz) + 25dbm (901mhz), 0/2.6v control, v dd = 2.85v *4 pin = 25dbm (1.9ghz) + 25dbm (1.901ghz), 0/2.6v control, v dd = 2.85v item symbol condition min. typ. max. unit insertion loss il 830 to 930mhz 0.35 0.50 db 1575.42mhz 0.40 0.55 db 1.92 to 2.17ghz 0.50 0.65 db isolation iso 830 to 930mhz 25 30 db 1575.42mhz 23 30 db 1.92 to 2.17ghz 20 30 db vswr vswr 50 1.2 1.4 ? switching speed tsw 5 10 s 1db compression input power p1db v dd = 2.85v 32 dbm harmonics 2fo *1 ?70 ?65 dbc 3fo *1 ?70 ?65 dbc 2fo *2 ?65 ?60 dbc 3fo *2 ?65 ?60 dbc input ip3 ip3 *3 55 60 dbm *4 55 60 dbm bias current idd v dd = 2.85v 150 190 a control current ictl vctl(h) = 2.6v 15 20 a
CXG1215UR - 4 - sony corporation package outline (unit: mm) sony code eiaj code jedec code package material lead treatment lead material epoxy resin solder plating copper alloy package structure uqfn-16p-01 package mass terminal section note:cutting burr of lead are 0.05mm max. pin 1 index c 0.1 s a-b 0.18 0.05 m s c c a-b s 0.05 s max0.02 + 0.09 16pin uqfn 9? plastic 9? 0.25 ? 0.03 x 4 2.3 5 1 4 12 9 8 16 13 2.3 s 0.4 0.1 : 0.9 0.55 0.05 4-r0.2 a b solder plating 0.14 0.4 + 0.09 0.14 ? 0.03 0.26 0.07 0.25 0.01g thermal die pad lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18m spec.
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